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ISL84524, ISL84525
Data Sheet March 2003 FN6042
Low-Voltage, Single Supply, 4 to 1 Multiplexer and DPDT Analog Switches
The Intersil ISL84524 and ISL84525 devices are precision, bidirectional, analog switches configured as a 4 channel multiplexer / demultiplexer (ISL84524) and a double pole / double throw (DPDT) switch (ISL84525) designed to operate from a single +2V to +12V supply. Both have an inhibit pin to simultaneously open all signal paths. ON resistance is 200 with a +5V supply and 500 with a +3V supply. Each switch can handle rail to rail analog signals. The off-leakage current is only 1nA at +25oC or 25nA at +85oC. All digital inputs have 0.8V to 2.4V logic thresholds, ensuring TTL/CMOS logic compatibility when using a single +5V supply. The ISL84524 is a 4 to 1 multiplexer device. The ISL84525 is a committed dual DPDT, which is perfect for use in 2-to-1 multiplexer applications. Table 1 summarizes the performance of this family. For higher performance, see the ISL43640 and ISL43410 data sheets.
TABLE 1. FEATURES AT A GLANCE ISL84524 4:1 MUX 190 170ns / 50ns 92 90ns / 40ns ISL84525 DPDT 190 170ns / 50ns 92 90ns / 40ns
Features
* Drop-in Replacements for MAX4524 and MAX4525 * ON Resistance (RON) Max, VS = 5V . . . . . . . . . . . . 200 * ON Resistance (RON) Max, VS = 3V . . . . . . . . . . . . 500 * RON Matching Between Channels. . . . . . . . . . . . . . . . . . <8 * Low Charge Injection . . . . . . . . . . . . . . . . . . . . . . 5pC (Max) * Single Supply Operation. . . . . . . . . . . . . . . . . . . +2V to +12V * Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . . .<3W * Fast Switching Action (VS = 5V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns * Guaranteed Max Off-leakage @ 5V . . . . . . . . . . . . . . 25nA * Guaranteed Break-Before-Make * TTL, CMOS Compatible * Available in 10 Ld MSOP Package
Applications
* Battery Powered, Handheld, and Portable Equipment * Communications Systems - Radios - Telecom Infrastructure - ADSL, VDSL Modems * Test Equipment - Medical Ultrasound - Magnetic Resonance Image - CT and PET Scanners (MRI) - ATE - Electrocardiograph * Audio and Video Signal Routing
RON & tON / tOFF 3V R ON 3V t ON / tOFF 5V R ON 5V t ON / tOFF PACKAGE
10 Ld MSOP
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" * Application Note AN557 "Recommended Test Procedures for Analog Switches"
* Various Circuits - +3V/+5V DACs and ADCs - Sample and Hold Circuits - Operational Amplifier Gain Switching Networks - High Frequency Analog Switching - High Speed Multiplexing - Integrator Reset Circuits
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL84524, ISL84525 Pinouts
(Note 1) ISL84524 (MSOP) TOP VIEW ISL84525 (MSOP) TOP VIEW
NO2 1 NO3 2 NO1 3 INH 4 GND 5 LOGIC
10 V+ 9 COM 8 NO0 7 ADD1 6 ADD2
NO1 1 COM1 2 NC1 3 INH 4 GND 5 LOGIC
10 V+ 9 COM2 8 NO2 7 NC2 6 ADD
4:1 MUX NOTE: 1. Switches Shown for Logic "0" Inputs.
DPDT
Truth Tables
ISL84524 INH 1 0 0 0 0 ADD2 X 0 0 1 1 ISL84525 INH 1 0 0 NOTE: 11V. ADD X 0 1 SWITCH ON NONE NCX NOX ADD1 X 0 1 0 1 SWITCH ON NONE NO0 NO1 NO2 NO3
Ordering Information
PART NO. (BRAND) ISL84524IU (524I) ISL84525IU (525I) TEMP. RANGE ( oC) -40 to 85 -40 to 85 PACKAGE 10 Ld MSOP 10 Ld MSOP PKG. NO. M10.118 M10.118
NOTE: Most surface mount devices are available on tape and reel; add "-T" to suffix.
Logic "0" 0.8V. Logic "1" 2.4V, with VS between 3V and
Pin Descriptions
PIN V+ GND INH COM NOX NCX ADDX FUNCTION System Power Supply Input (+2V to +12V) Ground Connection Digital Control Input. Connect to GND for Normal Operation. Connect to V+ to turn all switches off. Analog Switch Common Pin Analog Switch Normally Open Pin Analog Switch Normally Closed Pin Address Input Pin
2
ISL84524, ISL84525
Absolute Maximum Ratings
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V Input Voltages INH, NO, NC, ADD (Note 2) . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Output Voltages COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 20mA Peak Current NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 40mA
Thermal Information
Thermal Resistance (Typical, Note 3) JA ( oC/W) 10 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . 190 Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Moisture Sensitivity (See Technical Brief TB363) 10 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 2 Maximum Storage Temperature Range. . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (Lead Tips Only)
Operating Conditions
Temperature Range ISL8452XIU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 2. Signals on NC, NO, COM, ADD, or INH exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications +5V Supply
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, V INH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
Full V+ = 4.5V, I COM = 1.0mA, VNO or VNC = 3.5V (See Figure 5) V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V (Note 7) 25 Full 25 Full V+ = 5.5V, I COM = 1.0mA, VNO or VNC = 1.5V, 2.5V, 3.5V (Note 8) V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V (Note 6) V+ = 5.5V, VCOM = 4.5V, 1V, VNO or VNC = 1V, 4.5V (Note 6) V+ = 5.5V, VCOM = 1V, 4.5V, or V NO or VNC = 1V, 4.5V, or Floating (Note 6) Full 25 Full 25 Full 25 Full
0 -1 -10 -1 -25 -1 -25
2 -
V+ 150 200 10 15 15.5 1 10 1 25 1 25
V nA nA nA nA nA nA
RON Matching Between Channels, RON RON Flatness, RFLAT(ON) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM OFF Leakage Current, ICOM(OFF) COM ON Leakage Current, ICOM(ON)
DIGITAL INPUT CHARACTERISTICS Input Voltage High, V INH Input Voltage Low, VINL Input Current, I INH, IINL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON VNO or VNC = 3V, RL =300 , CL = 35pF, VIN = 0 to 3 (See Figure 1) VNO or VNC = 3V, RL =300 , CL = 35pF, VIN = 0 to 3 (See Figure 1) 25 Full 25 Full 90 40 150 200 120 180 ns ns ns ns V+ = 5.5V, V IN = 0V or V+ Full Full Full 2.4 -1 1.5 1.5 0.8 1 V V A
Inhibit Turn-OFF Time, tOFF
3
ISL84524, ISL84525
Electrical Specifications +5V Supply
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, V INH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified (Continued) TEST CONDITIONS VNO or VNC = 3V, RL =300, C L = 35pF, VIN = 0 to 3 (See Figure 1) RL = 300 , CL = 35pF, VNO = VNC = 3V, V IN = 0 to 3 (See Figure 3) CL = 1.0nF, VG = 0V, RG = 0 (See Figure 2) RL = 50 , CL = 5pF, f = 1MHz (See Figure 4) RL = 50 , CL = 5pF, f = 1MHz (See Figure 6) TEMP (oC) 25 Full 25 25 25 25 25 25 25 25 25 (NOTE 5) MIN 5 TYP 90 20 0.8 75 -85 4 14 6 20 12 (NOTE 5) MAX UNITS 150 200 5 ns ns ns pC dB dB pF pF pF pF pF
PARAMETER Address Transition Time, t TRANS
Break-Before-Make Time Delay, tD Charge Injection, Q OFF Isolation Crosstalk (Channel-to-Channel), (ISL84525)
NO or NC OFF Capacitance, COFF f = 1MHz, V NO or VNC = VCOM = 0V (See Figure 7) COM OFF Capacitance, CCOM(OFF) f = 1MHz, V NO or VNC = VCOM = 0V (See Figure 7) ISL84524 f = 1MHz, V NO or VNC = VCOM = 0V (See Figure 7) ISL84525 COM ON Capacitance, C COM(ON) f = 1MHz, V NO or VNC = VCOM = 0V (See Figure 7) ISL84524 f = 1MHz, V NO or VNC = VCOM = 0V (See Figure 7) ISL84525 POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 5.5V, V IN = 0V or V+, all channels on or off
Full 25 Full
2 -1 -10
-
12 1 10
V A A
NOTES: 4. VIN = input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25oC. 7. RON = RON (MAX) - RON (MIN). 8. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
Electrical Specifications +3V Supply
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, V AH = 2.4V, VAL= 0.8V (Note 4), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
Full V+ = 2.7V, I COM = 1.0mA, VNO or VNC = 1.5V (See Figure 5) V+ = 3.6V, VCOM = 1V, 3V, VNO or VNC = 3V, 1V (Note 6) V+ = 3.6V, VCOM = 3V, 1V, VNO or VNC = 1V, 3V (Note 6) V+ = 3.6V, VCOM = 1V, 3V, or VNO or VNC = 1V, 3V, or floating (Note 6) 25 Full 25 Full 25 Full 25 Full
0 -1 -10 -1 -25 -1 -25
-
V+ 400 500 1 10 1 25 1 25
V nA nA nA nA nA nA
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM OFF Leakage Current, ICOM(OFF) COM ON Leakage Current, ICOM(ON)
4
ISL84524, ISL84525
Electrical Specifications +3V Supply
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, V AH = 2.4V, VAL= 0.8V (Note 4), Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (oC) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS
PARAMETER DIGITAL INPUT CHARACTERISTICS Input Voltage High, V INH Input Voltage Low, VINL Input Current, I INH, IINL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON
Full Full V+ = 3.6V, V IN = 0V or V+ Full
2.0 -1
1.0 1.0 -
0.5 1
V V A
VNO or VNC = 1.5V, R L =300, CL = 35pF, VIN = 0 to 3 (See Figure 1) VNO or VNC = 1.5V, R L =300, CL = 35pF, VIN = 0 to 3 (See Figure 1) VNO or VNC = 1.5V, R L =300, CL = 35pF, VIN = 0 to 3 (See Figure 1) RL = 300, CL = 35pF, VNO or V NC = 1.5V, VIN = 0 to 3 (See Figure 3) CL = 1.0nF, VG = 0V, RG = 0 (See Figure 2) RL = 50 , CL = 5pF, f = 1MHz (See Figure 4) RL = 50 , CL = 5pF, f = 1MHz (See Figure 6)
25 Full 25 Full 25 Full Full 25 25 25 25 25 25 25 25
5 -
170 50 130 40 0.8 75 -85 4 14 6 20 12
300 400 200 300 300 400 1 -
ns ns ns ns ns ns ns pC dB dB pF pF pF pF pF
Inhibit Turn-OFF Time, tOFF
Address Transition Time, t TRANS
Break-Before-Make Time Delay, tD Charge Injection, Q OFF Isolation Crosstalk (Channel-to-Channel)
NO or NC OFF Capacitance, COFF f = 1MHz, V NO or VNC = VCOM = 0V (See Figure 7) COM OFF Capacitance, CCOM(OFF) f = 1MHz, V NO or VNC = VCOM = 0V (See Figure 7) ISL84524 f = 1MHz, V NO or VNC = VCOM = 0V (See Figure 7) ISL84525 COM ON Capacitance, C COM(ON) f = 1MHz, V NO or VNC = VCOM = 0V (See Figure 7) ISL84524 f = 1MHz, V NO or VNC = VCOM = 0V (See Figure 7) ISL84525 POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 3.6V, V IN = 0V or V+, all channels on or off
25 Full
-1 -10
-
1 10
A A
5
ISL84524, ISL84525 Test Circuits and Waveforms
C V+ C
V+
NO0 NO1-NO3 INH
ISL84524 COM VOUT
3V LOGIC INPUT 50% 0V tON
tr < 20ns tf < 20ns
LOGIC INPUT
ADD1, GND ADD2
RL 300
CL 35pF
C 90% SWITCH OUTPUT 0V tOFF VOUT 90% V+ NC NO INH LOGIC INPUT
V+
C
ISL84525 COM GND ADD VOUT
RL 300
CL 35pF
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for other switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) -----------------------------R +R
L ( ON )
FIGURE 1A. INHIBIT MEASUREMENT POINTS
FIGURE 1B. INHIBIT TEST CIRCUIT
C
V+
C
V+
NO0 NO1-NO3 ADD1 ADD2
ISL84524 COM INH RL 300 VOUT
3V LOGIC INPUT 50% 0V tTRANS
tr < 20ns tf < 20ns
GND
LOGIC INPUT
CL 35pF
C SWITCH OUTPUT 0V tTRANS ADD 90% VOUT 90% V+ NC NO
V+
C
ISL84525 COM INH RL 300 VOUT
GND LOGIC INPUT
CL 35pF
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for other switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) -----------------------------R +R
L ( ON )
FIGURE 1C. ADDRESS MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES
FIGURE 1D. ADDRESS TEST CIRCUIT
6
ISL84524, ISL84525 Test Circuits and Waveforms (Continued)
V+ C
3V LOGIC INPUT OFF ON 0V OFF RG NO or NC ADDX VOUT VG GND INH LOGIC INPUT Q = VOUT x CL CL COM VOUT
SWITCH OUTPUT VOUT
FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION
FIGURE 2B. TEST CIRCUIT
V+ C
C
VOUT V+
NO0-NO3
COM ISL84524 RL 300 CL 35pF
ADD1 ADD2 3V LOGIC INPUT 0V tr < 20ns tf < 20ns LOGIC INPUT
GND
INH
V+ SWITCH OUTPUT VOUT 0V tD 80% C
C
V+
NO NC
VOUT COM ISL84525 RL 300 CL 35pF
ADD LOGIC INPUT GND INH
Repeat test for other switches. CL includes fixture and stray capacitance. FIGURE 3A. MEASUREMENT POINTS FIGURE 3. BREAK-BEFORE-MAKE TIME FIGURE 3B. TEST CIRCUIT
7
ISL84524, ISL84525 Test Circuits and Waveforms (Continued)
V+ C SIGNAL GENERATOR
NO or NC
V+ C RON = V1/1mA
NO or NC
VNX 0V or V+ ADDX 0V or V+
COM
1mA
V1
0V or V+ ADDX
ANALYZER RL
GND
INH
COM
GND
INH
FIGURE 4. OFF ISOLATION TEST CIRCUIT
V+ C
FIGURE 5. RON TEST CIRCUIT
V+ C
SIGNAL GENERATOR
50
NO1 or NC1 COM1 NO or NC
ISL84525 0V or V+ ADD 0V or V+ IMPEDANCE ANALYZER
NO2 or NC2
ADDX
NC
COM
ANALYZER RL
COM2
GND
INH
GND
INH
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
8
ISL84524, ISL84525 Detailed Description
The ISL84524 and ISL84525 operate from a single 2V to 12V supply with low on-resistance and high speed operation. The devices are especially well suited to portable battery powered equipment thanks to the low operating supply voltage (2.7V), low power consumption (3W), low leakage currents (25nA max), and the tiny MSOP packaging. High frequency applications also benefit from the wide bandwidth, and the very high off isolation (75 dB) and crosstalk rejection (-85dB).
Power-Supply Considerations
The ISL8452X construction is typical of most CMOS analog switches, except that they have only two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 13V maximum supply voltage, the ISL8452X 15V maximum supply voltage provides plenty of room for the 10% tolerance of 12V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 2V. It is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance curves for details. V+ and GND also power the internal logic and level shifters. The level shifters convert the input logic levels to switched V+ and GND signals to drive the analog switch gate terminals. This family of switches cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration.
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and GND (see Figure 8). To prevent forward biasing these diodes, V+ must be applied before any input signals, and input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1k resistor in series with the input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not applicable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low RON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 8). These additional diodes limit the analog signal from 1V below V+ to 1V above GND. The low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages.
OPTIONAL PROTECTION RESISTOR FOR LOGIC INPUTS 1k ADDX 1k INH VNO or NC VCOM
Logic-Level Thresholds
This switch family is TTL compatible (0.8V and 2.4V) over a supply range of 2V to 11V. At 12V the VIH level is about 2.5V. This is still below the TTL guaranteed high output minimum level of 2.8V, but noise margin is reduced. For best results with a 12V supply, use a logic family that provides a VOH greater than 3V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation.
High-Frequency Performance
In 50 systems, signal response is reasonably flat even past 100MHz (see Figure 13). Figure 13 also illustrates that the frequency response is very consistent over varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch's input to its output. Off Isolation is the resistance to this feed through, while Crosstalk indicates the amount of feed through from one switch to another. Figure 14 details the high Off Isolation and Crosstalk rejection provided by this family. At 10MHz, Off Isolation is about 55dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance.
OPTIONAL PROTECTION DIODE V+
GND OPTIONAL PROTECTION DIODE
FIGURE 8. OVERVOLTAGE PROTECTION
9
ISL84524, ISL84525
Leakage Considerations
Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND.
Typical Performance Curves TA = 25oC, Unless Otherwise Specified
250 VCOM = (V+) - 1V ICOM = 1mA 200 85 oC 150 RON () RON () 25oC 100 -40 oC 50 225 200 175 150 125 100 75 140 120 100 80 60 80 70 85oC 60 50 40 -40oC 30 0 25oC -40oC 85 oC 25 oC V+ = 3.3V ICOM = 1mA
85oC 25 oC -40oC V+ = 12V
V+ = 5V
0 3 4 5 6 7 8 V+ (V) 9 10 11 12 13
2
4
6 VCOM (V)
8
10
12
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE
350 VCOM = (V+) - 1V 300 250 200 150 100 50 0 2 3 4 5 6 7 V+ (V) 8 9 10 11 12 -40 oC 85oC 25oC tOFF (ns) tON (ns)
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
120 110 100 90 80 70 60 50 40 30 20 10 2 3 4 5 6 7 V+ (V) 8 9 10 11 12 -40oC 85oC 25 oC VCOM = (V+) - 1V
FIGURE 11. TURN - ON TIME vs SUPPLY VOLTAGE
FIGURE 12. TURN - OFF TIME vs SUPPLY VOLTAGE
10
ISL84524, ISL84525 Typical Performance Curves TA = 25oC, Unless Otherwise Specified (Continued)
NORMALIZED GAIN (dB) V+ = 5V +3 0 GAIN -3 CROSSTALK (dB) VIN = 0.2V P-P -10 V+ = 3V to 12V -20 -30 -40 -50 -60 -70 -80 CROSSTALK -90 -100 -110 1k 90 100 110 100M 500M ISOLATION 20 30 OFF ISOLATION (dB) 40 50 60 70 80 10
VIN = 5VP-P
0 PHASE 45 VIN = 5VP-P 90 135 180 RL = 50 1 10 100 FREQUENCY (MHz) 600
PHASE (DEGREES)
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 13. FREQUENCY RESPONSE
1
FIGURE 14. CROSSTALK AND OFF ISOLATION
0.75 V+ = 5V 0.5 Q (pC)
0.25 V+ = 3.3V 0
-0.25
-0.5
0
1
2 VCOM (V)
3
4
5
FIGURE 15. CHARGE INJECTION vs SWITCH VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: ISL84524: 193 ISL84525: 193 PROCESS: Si Gate CMOS
11
ISL84524, ISL84525 Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1 E
INCHES SYMBOL MIN 0.037 0.002 0.030 0.007 0.004 0.116 0.116 MAX 0.043 0.006 0.037 0.011 0.008 0.120 0.120
MILLIMETERS MIN 0.94 0.05 0.75 0.18 0.09 2.95 2.95 MAX 1.10 0.15 0.95 0.27 0.20 3.05 3.05 NOTES 9 3 4 6 7 15o 6o Rev. 0 12/02
INDEX AREA
-B12 TOP VIEW 0.25 (0.010) GAUGE PLANE SEATING PLANE -C4X R1 R 0.20 (0.008) ABC
A A1 A2 b c D E1
L L1
A
A2
4X
e E L
0.020 BSC 0.187 0.016 0.199 0.028
0.50 BSC 4.75 0.40 5.05 0.70
A1
-He D
b
0.10 (0.004) -A0.20 (0.008)
C
SEATING PLANE
L1 N R
0.037 REF 10 0.003 0.003 5o 0o 15o 6o
0.95 REF 10 0.07 0.07 5o 0o
C a C L E1
C
R1
SIDE VIEW
-B-
0.20 (0.008)
CD
END VIEW
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12

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